Current monitoring and overcurrent trip circuits are typically used in high current voltage regulation IC's, including DC-DC switching converters. These circuits protect the IC, and/or the other circuits to which the regulator is supplying current, in applications such as computers, communications, and industrial machinery. Without over current monitoring, both the switching regulator itself and the circuits powered by the regulator may overheat and collapse when there is too much current being supplied to the load.
In a conventional DC-DC converter, a switching transistor (switches) is turned ON to pass a noisy input voltage to the output as a quiet, well regulated output voltage that is sourcing a large current. This current may be monitored a number of ways. A typical current monitor circuit has a current sensing element which provides an associated voltage signal that is sent to a comparator stage to decide whether the voltage signal is higher than some reference (voltage) value that is representative of an over-current threshold. The comparison is often made only after a certain time interval that allows signals to settle, known as the blanking time interval.
FIG. 1 shows a typical timing diagram for the blanking time and a pulse (PH) which controls a conventional DC-DC switcher, turning it on and off to pass or restrict current to the load. There are several cases, 1A-1C. FIG. 1A with a long PH (switcher ON) time interval case allows the current limit circuit much time after the blanking period, to operate and make a decision. However, cases 1B and 1C give the current limiting circuit very little time to operate and make a decision. This circumstance occurs when the switching cycle is very fast, and the switcher is ON only briefly.
FIG. 2a shows a prior art example of a “continuous time” high speed comparator that may be used as part of a current limiting circuit, similar to those used in many Texas Instruments DC-DC converter products.
FIG. 2b shows a discrete time current comparator, such as described in U.S. Pat. No. 6,147,518, that switches currents. The decision is made on the edge of an enable control signal.
FIG. 3 shows a block diagram of a conventional “track and latch” comparator architecture adapted to be used in data converters. A preamplifier is selectively enabled by a clock signal, and its output “tracks” the input while the second latch stage is simultaneous disabled and is controlled by the same clock signal. During the latch mode, starting at the rising edge of the clock signal, the latch stage is enabled and regeneratively amplifies the output of the preamplifier with nearly infinite gain (i.e. a decision will be made regardless), producing and holding the output logic decision.